ECC (i.e. Error Correction Code) can be used to detect and correct erroneous data by adding parity bits to data bits of a certain length. The conventional read and write processes for memory with error correction function are shown as FIGS. 1-2. FIG. 1 schematically shows a write process. A data array 1 is used to store data, and an ECC array 2 is used to store parity bits of ECC. When N-bit data are written into the memory from the system, M-bit parity bits are generated by an ECC encoding module 3 using the N-bit data, and then the N-bit data together with the M-bit parity bits are written into the corresponding memory arrays. The data length N is greater than zero, and is less than or equal to the data length for performing one read-write operation in the memory. The length M of the parity bits is greater than zero, and its value depends on the selected ECC algorithm.
FIG. 2 schematically shows a read process. N-bit data and M-bit parity bits are read from the corresponding memory arrays, and then are transferred to an ECC decoding module 4 after being amplified. The ECC decoding module 4 can detect and correct erroneous data, and read the corrected N-bit data.
From the write process in FIG. 1, it can be known that when the ECC encoding module 3 generates M-bit parity bits, the data length N are required, which is determined by the selected ECC algorithm. Nevertheless, with respect to memory, the lengths of the valid input data are not unchanged. For example, there are following specifications in Dynamic Random Access Memory (DRAM): if there is Burst Chop Mode (hereinafter referred as “BC mode”), the data length will vary such that the data length is less than N; or for structure with different data lengths, for example in the modes of X4, X8, X16 and so on, the data length will vary as a function of the external control such that the data length is not equal to N. Once an ECC algorithm is selected, the data length required by the corresponding ECC encoding module is determined, and if the data length varies, the parity bits of ECC cannot be generated successfully. Where a minimum data length could be found under all the constraints that may occur, and according to such a minimum data length, the ECC algorithm is selected, all of the modes can be supported. But if the minimum data length is 8, even for the most efficient Hamming code, at least 4-bit parity bits are required, which may increase at least 50% of the memory array area in order to store parity bits of ECC. This leads to a dramatic increase in the cost of memory, and reduces the flexibility and efficiency in the selection of ECC algorithm.
Therefore, there is a need to provide a memory with error correction function that is compatible with different data lengths.